The last fpga classes were taught shortly after moving to our current location. Instructor made the critical mistake of not listing any pre reqs for the class. 1st class filled the Lecture Hall. Student experience in any kind of logic design ranged from none to senior designer. By the 3rd - 4th class attendance had gone down to a core of ~6 students. Classes got bogged down in logic design basics.
VHDL and Intel / Altera Quartus (free version) were used. Unfortunately at the time not all of Quartus worked. Nothing like being on the flat end of the learning curve following a tutorial, successfully completing 80% of the project and then things stop working. Very frustrating. Schematic capture did not generate code - no error msgs.
Some resources are listed in this post:
In the Mouser donation list I included the Intel MAX 10 eval brds for classes.
(status of donation is unknown at this time)
Some other details / questions -
My understanding of the current honorarium system is this will be seen as a series of classes and eligible for only 1 honorarium payment.
Do you plan on recording the classes and labs?
What are you considering for a txt bk?
Verify that what you want to do in ModelSim works - no surprises.
We could look into putting ModelSim, Quartus, etc. on the pcs in the new Computer Lab.
Thanks for offering to teach on this. If there’s enough ongoing interest, we can put together a FPGA SIG.