I am working on a VHDL class to start next month. This is like a 3 hour college class so it will run for about 12 weeks. It will be an online, interactive, instructor led class. It will cover language basics and the ModelSim simulator. There is a text book and there will be assignments. The class is open to all, so feel free to pass this on. I want to cover 2 one hours lectures and 2 one hour labs a week.
Fee - $25 members, $50 non-members
Instructor – Dan Ludden BSEE
If you are interested please message me and include the following survey.
Class time – afternoon or evening
Class format – two days a week (two hours), four days a week (one hour)
Programming experience – I understand basic programming (loops, if/else, etc)
Electronic experience – I have a basic understanding of registers, logic, etc
We need more FPGA/CPLD stuff at DMS for sure thanks for stepping up!
I hate to be that guy, but why VHDL vs Verilog?
I hear VHDL is more math like definitions and Verilog is more similar to modern programming, languages and as crosstraining is easier a lot of industry is leaning Verilog.
Verilog is more like using C where you can easily shoot yourself in the foot because the language lets you. You can get code to do something faster since it’s more concise, but it may not be deterministic in the way you planned on. Shallow learning curve compared to VHDL, but even after things seem to work there’s still a curve in handling validation, determinism, and synchronous items can be problematic with blocking assignments. Most of the education programs I encountered started with Verilog but after getting students primed with concepts ended up actually using VHDL
VHDL is more like old Ada and Pascal. Extremely verbose, but once the code is running it’s generally doing what you want unless you really screwed the pooch. Steeper learning curve, but once things start working generally easier to work with.
The last fpga classes were taught shortly after moving to our current location. Instructor made the critical mistake of not listing any pre reqs for the class. 1st class filled the Lecture Hall. Student experience in any kind of logic design ranged from none to senior designer. By the 3rd - 4th class attendance had gone down to a core of ~6 students. Classes got bogged down in logic design basics.
VHDL and Intel / Altera Quartus (free version) were used. Unfortunately at the time not all of Quartus worked. Nothing like being on the flat end of the learning curve following a tutorial, successfully completing 80% of the project and then things stop working. Very frustrating. Schematic capture did not generate code - no error msgs.
Some resources are listed in this post:
In the Mouser donation list I included the Intel MAX 10 eval brds for classes.
(status of donation is unknown at this time)
Some other details / questions -
My understanding of the current honorarium system is this will be seen as a series of classes and eligible for only 1 honorarium payment.
Do you plan on recording the classes and labs?
What are you considering for a txt bk?
Verify that what you want to do in ModelSim works - no surprises.
We could look into putting ModelSim, Quartus, etc. on the pcs in the new Computer Lab.
Thanks for offering to teach on this. If there’s enough ongoing interest, we can put together a FPGA SIG.
That’s the point of the survey. If I need to I will put together a hardware for programmers prereq. I want to teach what everyone needs and I don’t want people being bored if I need to go over basics.
I’ll worry about the honorarium if we have enough interest.
The class will be online (I want to start it sooner than I would want to come to an in person class);
Hardware - This is a language course so there is no hardware. That’s the next course. ModelSim is from Altera(Intel) so I assume we will use their hardware when we get there. I’ve never used the free version of Quartus but I spent all of yesterday making sure that I can load ModelSim and get it to work.
Book - Designers Guide to VHDL
As for dropouts, you have to buy a book and I am charging for the class. It will be on a paid Moogle server. This allows me to record the class among other things.
I am hoping to teach two follow on courses - instantiation and test benches.
