Does anyone know if there’s a VHDL/Verilog simulator at the space to use and is there anyone to teach it?
Altera (Intel)'s Quartus Prime Lite is available for free.
Viewlogic speedwave was weapon of choice back in the day when I did such. But like Chris points out, the FPGA silicon providers have options, with my favorite two FPGA being Altera (now owned by Intel evidently) and Xilinx, without question.
Also, simulating is good, but for some designs, depending on complexity, its a good idea to look at some floorplanning for how the back end tool plans to lay out your design on the specific device chosen. This would be true in situations where you have a lot of combinational logic between each pipe, and need to be sure there are enough nearby combinational elements for each large operation, and the device is not having to stretch key operations in a funny way to fit the device’s limitations. Or another approach (and my preference) is to just start out with way oversized device. Then you don’t have to worry so much, and you have room to grow your feature set.
Get support when selecting your device from appropriate FAE. And tell them you are way early in your design, and want room to grow starting out. They will be happy to recommend an nice, oversized, and expensive device. But you can rock with too big for your prototypes, then shrink it down if you need to hit some volume. Pick a nice scaleable device family with numerous sized in a given form factor and be sure they are pin for pin. This will ensure you have room to scale up and scale down as could be necessary later. Then, you just simply spec in the appropriate size when all the feature decisions are finalized.
Verilator and gpl-cver are very capable simulators. I use gtkwave to view the resulting VCD output.
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Glad you mentioned GPL’d tools. I was initially looking at http://ghdl.free.fr/ since one can debug in ddd(1) and edit in vim(1); my usual workflow. It also supports using gtkwave.
My thought was deploying a build/vhdl sim grid at the space and having that availalbe over the computers in the interactive computer museum or via the publix grid.
Ultimately my own projects are based on building a SoC style system centered on FPGAs to create upgradable hardware system in the same idea as virtual machines has to servers. After all, my understanding is the cost about equals at this point between the physical chip one is coding into the fpga as the fpga but… the fpga is able to go beyond that and be upgradable with new code uploads.
You might check out the C-One …
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I’d recommend something a bit more modern, since tool support is always a concern:
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Terasic also has some nice low cost Altera offerings
http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=234&No=1021
For a no-install cloud-based simulation environment, there is EDA Playground by Doulos. I think this was originally an independent effort that got snapped up by Doulos. I’m not sure if it’s practical for big designs, but it’s fun. There are both commercial (Aldec, Synposis VCS) and open source tools (Icarus, etc) available. Or can do HDL coding in python using MyHDL. The waveform viewer is rather limited.
There’s a collaboration feature that’s listed as beta that might be useful for maker classes.
I had a good bit of fun playing with verilog to learn a bit, as I’m almost solely a VHDL guy.
https://www.edaplayground.com/
For the open source purists (and unrelated to EDA Playground), there is an open source tool set that can synthesize and generate bit streams for the Lattice iCE40 family. This uses the opens source yosys synthesis tool (which is supported by EDA Playground)
http://www.clifford.at/icestorm/
Create your iCE40 designs graphically (schematically), if you don’t want to write any code.
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