@artg_dms and I where talking about building a 4 bit PWM generator at the Tech Gathering last night., which by the way was a complete success …
We were going over what we might use. I found this diagram today. Anyone have any suggestions?
It has a downfall however that it can never be fully at 100%…
What would you suggest?
It is a really good solution but it isn’t considered digital. We wanted to be able to control it with a digital input. Yes, we could use a resistor ladder with it but I think we might be able to do it with just 74 series
Went looking thru my notes and found this:
http://spaennare.se/pwmdig.html#chap62
He uses CD4k series parts. A simple 4 bit version can be built using 74xx85 4 bit comparator and 1/2 of 74xx393 4bit bin cntr. Ckt has some short comings. Can wire to achieve 0% OR 100% - probably there’s a way to get both. Will never do an exact 50%. You’re cntng 0-15 so there’s never an exact center point.
Built ckt using 8 bit cntrs and comparators. Cntrs were limited to 0-59 cnts (6 bits). 6 bits determined the pwm and also decoded to 2x 7 seg rg led splys. Got really messy fast. Ckt build (minus decoder) mostly worked - watching the pwm on scope had occasional glitch. Idea was to implement in VHDL and pgm fpga. Purely a design what if exercise.
Moving on - wrote (ugly!) pgm on arduino uno. Much easier and works. Clock digits index an array which has pwm values. Drives 2x 7 seg rgb dsply. Interesting to watch dsply go from one color to the next in 60 steps.~QED.
Bear in mind that an ATtiny / AVR processor may actually be less expensive than the discrete components. And, they typically have two built-in clocks.
Need 9 pwm chnls for project. Uno has 6 and Mega has 15 - w/ plenty of left over I/O. Mega could easily accommodate design w/ plenty of room for updates and improvements - the never ending “WIBNI List”. PWM color control is at the digit pair level. An Uno blasting out serial streams to strings of TLC5941s would allow for color control down to individual segments of each digit. And for some very entertaining pgmng.
As mentioned above this was an exercise in taking hrdwr/sftrwr functions into VHDL. Interesting note - I was able to enter the 6 bit to 2x 7 seg decoder into Quartus using case/switch. Quartus came back and indicated decoder would take up 90+% of the fpga we were going to use for the class. And at that time the part was getting ready to go EOL.
