@bpamplin - thanks for the kind words. Here’s the ad hoc review of Brady’s design that I sent to him via PM. Kudos to Brady for diving headlong into creating a design with a new set of schematic/pcb tools and learning on the fly.
[begin reposted review]
Thanks for uploading and linking the latest EasyEDA design. I was able to clone/copy the design and am playing around with the routing a bit.
A few bits of (intended to be) constructive feedback regarding the design.
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The Pi Pico symbol doesn’t have pin numbers, but instead duplicates the pin labels as pin numbers. Convention for schematics and PCBs is to use pin numbers. This makes it much easier when probing a board, as one can find a specific pin numbers without a schematic reference. It may be that a pre-existing Pi Pico symbol was used that didn’t have pin numbers.
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Only 2 of the GND pins on the Pico is connected, the rest are not connected. It is strongly encourage to connect all power and GND pins on a device - especially the GNDs.
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Cosmetic/style - In a schematic, by convention, GND symbols shouldn’t have a ‘sideways’ orientation. Also preferable for power symbols
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Mounting holes in corner of board are preferred to be aligned and uniformly spaced from board edge
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Leave trace-free clearance around mounting holes, so that traces aren’t underneath metal mounting screw heads
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Traces coming out of part pad should come straight out from pad, then bend. Also, note how close trace is to adjacent pin pad [measured 7.5 mils here]
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Thinner traces can be used for routing signals. Current design uses 1.0 mm traces. This prevents routing traces between Pico pads. Measured the inter-pad gap to be 30 mils, leaving space for a 10 mil trace with 10 mil gap on each side.
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After all routing is done, it’s a good idea to do a copper pour for GND. Although this can be tricky to make sure that there aren’t any non-connected copper islands in the pour.
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The ease or difficulty of most PCB layout is a function of component placement, especially so on a 2 layer board. On a 2 layer board, I like to minimize the power supply rail routing distance between components to make it easier to connect with thick traces or small copper pours. The signal routing is less critical for the relatively low speeds of most of the peripherals on this board.
IIRC from your comments, this board was auto-routed. While it is an ‘easy’ button for hobbyist work, most of my PCB design buddies avoid it. If they do use it, there’s a lot of setup of routing constraints to insure that the best results can be achieved.
Speaking of constraints (or classes), I wasn’t able to find any way to set any. For example, it would be nice to be able to have a power trace type/class with 1 mm width and a signal trace class with 0.254 mm (10 mils). Then the trace type could be selected without having to enter the specific width when changing.
OK, I’ve gone overboard here. You’ve done a great job and I don’t mean to diminish your accomplishments at all. Just giving some feedback.
For background, I’m not a PCB designer. I’ve done a few very simple boards myself. But, I’ve done a lot of very complex FPGA designs with layer counts up to 18. For those designs I’ve worked with gifted PCB designers, in a role where I give a layout guide with some of the above constraints and a bunch of others. So, I know what I want in a PCB design but that doesn’t mean I’m skilled enough to drive the tools to get what I want.
I have attempted to update the design to use pin numbers for the Pico, and have updated the schematic. But I’ve been completely stumped regarding how to make the corresponding change in the PCB footprint. I can’t even locate the symbol in a way that I can clone/copy it and make the changes.
I found a user-contributed footprint that looks identical and made the modifications and saved it. But I can’t find it anywhere to substitute in your cloned design - I’m still stumbling my way through EasyEDA
I’m open to any suggestions you may have.
FYI, here’s what the update Pico schematic symbol looks like with: pin numbers instead of names, all GNDs connected, power connections made ‘vertical’
Hope this wasn’t TL;DR
[end reposted review]